1. Field of the Invention
The present invention generally relates to testability analysis systems and methods, designs for testability system and method and, more particularly, to a testability analysis system and method, and a design for testability system and method that can analyze controllability and observability with a logic built-in self testing mechanism at the level of a hardware functional description independent of architecture for a large scale integrated circuit.
2. Description of the Related Art
As an integrated circuit becomes more large-scaled and performs more complicated operations, more time is required to design a test pattern for testing the integrated circuit. In some cases, the required test design time exceeds time to design the integrated circuit.
Accordingly, it is indispensable to prepare a DFT (Design For Testability) whereby a large-scale integrated circuit is provided with some measures for reducing some burdens on test design and test implementation at a logic design level.
Recently, the DFT technique has adopted BIST (Built-In Self Test). In the BIST, a circuit for automatically testing an integrated circuit is built in the integrated circuit. By using the BIST, it is possible to efficiently test the integrated circuit even while the integrated circuit is being manufactured and is being operated in the field.
The BIST has less constraints with respect to the length of a test sequence because the number of BIST scan chains can be increased over the number of extent chains. On the other hand, it is required to suppress an increase of the chip size as much as possible. There are some methods to fulfill the testing requirement, typically an exhaustive test and a random test. The above two methods can use simple hardware such as an LFSR (Linear Feedback Shift Register) to generate a test sequence. Especially, the LFSR for generating random patterns is called PRPG (Pseudo Random Pattern Generator). Regarding evaluation of test results, there are several methods. In one method, whenever one test result is obtained, the test result is compared with an expected value. However, the BIST adopts not this method but a different analysis method. In the BIST, after a collection of test results are compressed by using a multi-input LFSR, the compressed test results are compared with a reference value (Signature Analysis). (ref. Japanese Laid-Open Patent Application No. 05-241882, and Japanese Patent No. 2711492) However, the signature analysis has a problem in that when an X (an unstable signal condition) is propagated to the multi-input LFSR, the reference value, which is called the signature, is collapsed.
Regarding test design using LogicBIST (Logic Built-In Self Test) in an integrated circuit, a conventional design flow is as follows. First, a netlist dependent upon a technology is generated by a logic synthesis from a hardware functional description independent of architecture. Then after a scan path test mechanism and a LogicBIST controller are added to the netlist, a fault simulator examines fault analysis and evaluates the fault coverage (fault detection rate). If the fault coverage is not sufficient, the controllability and the observability are evaluated based upon a report offered by the fault simulator and the netlist. Based upon the evaluation result, an appropriate testing circuit may be added or the hardware functional description may be modified in some cases. Here, the fault coverage in the LogicBIST decreases mainly because of the difficulty of detecting faults by the random pattern test that the PRPG in the Scan-Based LogicBIST executes.
According to such a conventional LogicBIST insertion flow, there arise some problems with respect to the controllability and the observability. First, the controllability and the observability cannot be evaluated without the fault simulator. Since a CAD tool is provided for each of a logic synthesis, a scan path insertion, a LogicBIST insertion and a fault simulator execution, it is necessary to consider total time to run the individual CAD tools. Second, it is difficult to analyze the controllability and the observability because the controllability and the observability analysis must be examined from the netlist being at the gate level dependent upon the technology. Third, it is difficult to incorporate the analysis result into the hardware functional description independent of the architecture. Fourth, if the testing circuit is inserted in the netlist after analyzing the controllability and the observability, the hardware performance becomes degraded.
On the other hand, Japanese Laid-Open Patent Applications No. 06-103101 and No. 08-15382 disclose a LogicBIST using LFSR.
In a technique according to Japanese Laid-Open Patent Application No. 06-103101, the testability is analyzed for a netlist being at the gate level so as to improve the fault coverage.
However, in the technique, the testability is not analyzed at the level of a hardware functional description independent of architecture.
A technique according to Japanese Laid-Open Patent Application No. 08-15382 is related to measures for the X (an unstable signal condition) propagation problem on the LogicBIST method and measures for a netlist being at the gate level by the simulation forcing the random patterns. However, the technique cannot be used to check the X propagation at a level of a hardware functional description independent of architecture.